In order to improve the display effect of a display device, more and more people start to pay attention to the design of a narrow frame for a display device. Especially for a spliced screen for large-screen outdoor display, a display device with a narrow frame can effectively reduce the width of a spliced gap in a spliced screen, thereby improving the overall display effect significantly.
In the prior art, manufacturing of a display with a narrow frame is generally realized by compressing a process margin to the limit, wherein a very important technology is a Gate Driver on Array (GOA) technology, which has achieved mass production. A gate switching circuit is integrated into an array substrate of a display panel by using the GOA technology, to form scan driving for the display panel, thus a gate driver integrated circuit may be omitted. This can not only reduce production cost in two aspects of material cost and manufacturing process, but also realize symmetry of two sides of a display panel and beautiful design of a narrow frame. The configuration of an existing display panel may be shown as in FIG. 1, wherein a GOA circuit 11 is symmetrically arranged at two sides of an effective display area 12. The microstructure of a portion of the GOA circuit 11 may be shown as in FIG. 2a. It can be clearly seen that, the area of the GOA circuit 11 may be further divided into a Thin Film Transistor (TFT) area 111, a capacitor area 112, and a lead-wire area 113 for connecting with the display area 12 to output a row-driving signal. The circuit structure of the capacitor area 112 may be shown as in FIG. 2b, wherein a transistor T in the TFT area 111 which is closest to an end of the capacitor area 112 is used for outputting a gate row-driving signal, and a source-drain metal layer and a gate layer which are connected to the transistor T are respectively taken as two ends of a capacitor C. FIG. 3 is a cross-sectional view of FIG. 2a taken along line A-A. It can be seen that, the lead-wire area 113 includes a gate layer 31, a gate-insulating layer 32, a resin layer 33, and a passivation layer 34. The capacitor C is formed between the source-drain metal layer located in the capacitor area 112 and the gate layer 31. The function of the capacitor C is to remove noise of the GOA circuit to ensure stability of the GOA circuit. However, the disadvantage thereof lies in that, in order to meet the specification of a capacitor, the length of the capacitor area 112 is generally made to be relatively large (as shown in FIG. 2a). Thus, the sire of the GOA circuit is limited, making it difficult for a frame of a display device to further narrow down.